Evaluating Branch Predictors on an SMT Processor

Simultaneous multithreading (SMT) provides significant increases in microprocessor throughput by issuing instructions from multiple threads per clock cycle. SMT can be realized in a wide-issue superscalar with a modest increase in resources, because much of the hardware is shared among the multiple thread contexts. Branch prediction accuracy, a key component of microprocessor performance, can suffer greatly from destructive interference caused by multiple threads sharing the same branch prediction hardware. Although SMT processors are able to hide branch latencies by scheduling instructions from other threads, branch prediction accuracy is still important in SMT processors to reduce latencies of individual threads and to provide a diverse mix of threads to the instruction scheduler. This paper evaluates several wellknown branch prediction schemes, and examines some modifications to address problems caused by sharing of branch prediction hardware in SMT.